This invention is in the field of integrated circuits, and is more specifically directed to reference voltage circuits therein.
As is well known in the field, many modern integrated circuits incorporate voltage detection and comparison circuits for comparing the voltages applied to or generated within the circuits against a reference level. Many modem integrated circuits utilize on-chip voltage regulators to generate internal bias voltages that are stable over variations in temperature, power supply voltage, and processing parameters. Additionally, voltage detection and comparison circuits are sometimes used in determining the operating range within which an externally applied power supply voltage is biased in modern integrated circuits that can operate in either a low power supply voltage range (e.g., 3.3 volts.+-.10%) or a higher power supply voltage range (e.g., 5 volts .+-.10%). Each of these types of circuit require a stable reference voltage to effect proper comparison and detection, as the comparisons carried out by these circuits are against absolute voltage levels (rather than as a differential comparison).
Bandgap reference circuits constitute one popular type of conventional reference voltage circuit. In general, bandgap reference circuits produce a reference voltage that depends upon two circuit elements with complementary temperature coefficients. Typically, the bandgap reference voltage depends upon the base-emitter voltage of a bipolar transistor (which may be a parasitic bipolar device in integrated circuits that are fabricated according to metal-oxide-semiconductor, or MOS, technologies) and also upon either the resistance value of a diffused resistor or upon a MOS transistor threshold voltage. Since the base-emitter voltage of a bipolar device has a temperature coefficient that is opposite from that of either of a differential base-emitter voltage of two bipolar transistors, a reference voltage that is generated from the combination of these characteristics can be quite stable over temperature. Accordingly, bandgap reference circuits are widely used in modem integrated circuits that require a stable reference voltage for internal voltage detection and comparisons.
Particularly in integrated circuits that detect the levels of the applied power supply voltage, it is important that the reference voltage circuits rapidly begin operation upon power-up of the integrated circuit. If a reference voltage circuit does not rapidly begin operation on power-up, it is possible for the integrated circuit to enter an unstable or indeterminate operating mode. For example, delayed power-up of the reference circuit may cause the incorrect detection of the power supply voltage operating range and, as a result, misconfiguration of internal circuits that are to be configured according to the power supply level. Other failures due to delayed generation of a reference voltage are well known in the art.
Accordingly, the use of power-up detection circuits to generate a signal upon power-up of the integrated circuit, and the application of these signals to initiate the operation of reference voltage circuits upon power-up, is known in the art. Referring now to FIG. 1, the construction and operation of an example of a conventiolal bandgap reference circuit in combination with a startup circuit for rapidly initiating operation of the bandgap reference circuit, according to the prior art, will now be described by way of background.
Bandgap reference circuit 10 in this conventional example is arranged as multiple current mirror legs, each including a bipolar transistor. The output leg of bandgap reference circuit 10 includes the series connection of the source/drain paths of p-channel transistors 12p and 14p; the source of transistor 12p is biased to power supply voltage V.sub.dd, and the drain of transistor 14p is connected to a resistor divider of resistors 16, 18. Resistors 16, 18 (as well as the other resistors in bandgap reference circuit 10), are preferably diffused resistors formed in p-type regions in the substrate of the integrated circuit within which bandgap reference circuit 10 is realized. P-n-p bipolar transistor 20 has its emitter connected to resistor 18, at the opposing end of the resistor divider, and has its base and collector at ground. The output of bandgap reference circuit 10 on line VREF is taken from the node between resistors 16, 18 in the resistor divider of this leg.
Two additional current mirror legs in bandgap reference circuit 10 are also provided. The middle leg includes the series source/drain connection of p-channel transistors 22p, 24p, with the source of transistor 22p at power supply voltage V.sub.dd and the drain of transistor 24p connected to one side of resistor 26. In this middle leg, n-channel transistor 28n has its source/drain path connected between resistor 26 and resistor 29. P-n-p bipolar transistor 30 has its emitter connected to resistor 29, and its base and collector at ground. The first leg of bandgap reference circuit 10 also includes series source/drain connection of p-channel transistors 32p, 34p, with the source of transistor 22p at power supply voltage V.sub.dd. In this leg, the drain of transistor 34p is connected to the drain of n-channel transistor 38n at node NBIAS; the source of transistor 38n is connected to the emitter of p-n-p bipolar transistor 40, which has its base and collector at ground.
The current mirroring in bandgap reference circuit 10 arises from the interconnection of the gates of transistors in the various legs. In this example, the gates of p-channel transistors 12p, 22p, 32p are connected in common at node PBIAS1, which is connected to the drain of transistors 24p. The gates of p-channel transistors 14p, 24p, 34p are connected in common at node PBIAS2, which is connected to the node between resistor 26 and the drain of transistor 28n. As illustrated in FIG. 1, the body nodes of transistors 14p, 24p, 34p are biased to their respective sources (rather than to V.sub.dd, as is the case for transistors 12p, 22p, 32p). The voltages established at nodes PBIAS1, PBIAS2 may be forwarded to other circuits in the integrated circuit within which bandgap reference circuit is deployed, if desired, as illustrated in FIG. 1. The gates of transistors 28n, 38n are connected in common at node NBIAS. Additionally, capacitor 39 is connected to node NBIAS, to provide common mode noise rejection relative to any noise that may appear at the bases of bipolar transistors 20, 30, 40.
In normal operation, bandgap reference circuit 10 uses the mirrored currents to establish a stable voltage at node VREF. Current that is conducted through the first leg of transistors 32p, 34p, 38n, 40 is mirrored through the second leg of transistors 22p, 24p, 28n, 30, and resistors 26, 29. The voltages that are established at nodes PBIAS1, PBIAS2 by this current mirror operation similarly bias transistors 12p, 14p, establishing a current through the output leg of transistors 12p, 14p, 20 with resistors 16, 18. The voltage drop across resistor 18 and transistor 20 generated by this current sets the output reference voltage on line VREF. The voltage on line VREF thus depends upon the base-emitter voltage of transistors 20, 30, 40, and upon the resistance of diffused resistors 18 and 29. Because the temperature coefficient of the base-emitter voltage of the bipolar transistors varies in an opposite fashion from the resistance of diffused resistors 16, 18, 26, 29, the output reference voltage at line VREF will be relatively stable over temperature, as is known in the art.
The normal operation of bandgap reference circuit 10 described hereinabove commences upon the conduction of current through the first leg of the current mirror, namely through the source/drain paths of transistors 32p, 34p, 38n, and through bipolar transistor 40. According to the conventional arrangement of FIG. 1, bandgap reference circuit 10 initiates such conduction through the operation of startup circuitry that biases node NBIAS upon receipt of an active high signal on line RID from power-up reset circuitry elsewhere in the integrated circuit, indicating the power-up of power supply voltage V.sub.dd.
Line RID is applied to a series of inverters 51, 53, 55, with the output of inverter 55 applied to the gate of p-channel transistor 50. Transistor 50 has its source/ drain path connected between node NBIAS and the drain of p-channel transistor 44p at node TO. Transistor 44p has its source/drain path connected in series with that of p-channel transistor 42p between power supply voltage V.sub.dd and node TO; the gate of transistor 42p is at ground, while the gate of transistor 44p is connected to one plate of capacitor 60, the other plate of which is at ground. P-channel transistor 48p has its drain connected to node TO, its source connected to power supply voltage V.sub.dd, and its gate driven by the output of inverter 53. Node TO is also connected to the gate of p-channel transistor 56p, the source of which is connected to capacitor 60 and the drain of which is at ground. P-channel transistors 52p, 54p have their source/drain paths connected in series between power supply voltage V.sub.dd and the source of transistor 56p, and have their gates controlled by the bias voltages PBIAS1, PBIAS2, respectively.
The operation of this circuitry in initiating the operation of bandgap reference circuit 10 in response to a power-up event will now be described. Prior to receiving the power-up signal, line RID is inactive low, and as such the gate of transistor 50 is at the level of power supply voltage V.sub.dd (from inverter 55), and transistor 50 is off. Transistor 48p is turned on by the low level at the output of inverter 53, and as such connects the level of power supply voltage V.sub.dd to node TO. At this time, capacitor 60 is discharged, generally through the tanks or wells of transistors 54p, 56p, to a voltage that is at least a p-channel threshold voltage below power supply voltage V.sub.dd. As a result, transistor 44p is turned on, permitting the level of power supply voltage V.sub.dd to also be applied to node TO through transistors 42p, 44p. Of course, prior to receiving the power-up signal on line RID, the level of power supply voltage V.sub.dd will be ramping from a low level toward its eventual high voltage. At this time, no conduction is occurring through any of the current mirror legs of bandgap reference circuit 10.
Upon the power-up detection circuit (not shown) issuing an active pulse on line RID in response to detecting the powering-up of power supply voltage V.sub.dd, this high level pulse will ripple through inverters 51, 53, 55, with the output of inverter 55 driving a low logic level at the gate of transistor 50, turning it on. The level of power supply voltage V.sub.dd that is present at node TO (through operation of transistors 42p, 44p, 48p) is then applied to node NBIAS, turning on transistor 38n and initiating conduction through the first current mirror leg of bandgap reference circuit 10. The current conducted through transistors 32p, 34p, 38n, 40 is then mirrored by the other legs of bandgap reference circuit 10, resulting in the establishment of the reference voltage on line VREF. Bias voltages are also established on lines PBIAS1, PBIAS2, as noted above.
After power up, the pulse on line RID ends, returning the output of inverter 55 back to a high level, turning off transistor 50 so that the voltage at node NBIAS is determined solely by the operation of the current mirror in bandgap reference circuit 10. The end of the pulse on line RID, via inverter 53, also turns on transistor 48p, forcing node TO high and turning off transistor 56p. Additionally, the establishment of bias voltages on lines PBIAS1, PBIAS2 cause transistors 52p, 54p to conduct, in a similar manner as in the current mirror legs of bandgap reference circuit 10. This conduction raises the voltage at capacitor 60 (transistor 56p being off), which turns off transistor 44p, to prevent parasitic conduction.
This operation has been observed to rapidly turn on bandgap reference circuit 10 upon power-up, with startup occurring within a few microseconds from the pulse on line RID. However, power-up situations have been observed in which the power-up detection circuit does not respond and generate the active pulse on line RID. Such situations include the powering-up of the circuit after a brief power-down interval. In addition, because the ramp rate of power supply voltage V.sub.dd on power-up is not specified, wide variations in actual system powering-up can occur, not all of which are always detectable by conventional power-up detection circuits. Without receiving an active power-up detection pulse on line RID, bandgap reference circuit 10 will not quickly establish a reference voltage on line VREF, as only parasitic conduction will at most be present through the current mirror legs if the startup circuitry does not initiate conduction. This parasitic conduction is insufficient to initiate operation of bandgap reference circuit 10 for many milliseconds, if not seconds, after power-up of power supply voltage V.sub.dd. This delayed operation in the generation of the reference voltage on line VREF can result in the integrated circuit entering an indeterminate or incorrect state. This can cause not only erroneous operation of the integrated circuit, but can also, in some circumstances, result in catastrophic failure of the device.